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Speaker: Prof. Taiyun Chi (Rice University)

Title: Toward AI-Assisted Analog and RF IC Design Automation

Abstract: LLMs have advanced rapidly over the past three years, with frontier systems now supporting trillion-scale parameter counts, million-token context windows, multimodal inputs/outputs, stronger reasoning, coding, computer use, and agentic workflows. At the same time, the way we work with LLMs has shifted accordingly, from prompt engineering to context engineering, and more recently to harness engineering. These advances and paradigm shifts have enabled many great successes in “AI for X,” especially in coding. This talk will present our group’s recent progress toward integrating LLMs into analog and RF IC design, a field that has conventionally remained manual, time-consuming, and dependent on deep domain expertise. We will discuss what today’s AI systems can do, where they still fail, and which directions appear most promising for analog and RF IC design automation. I will also cover AI techniques beyond LLMs that enable fast design-space exploration and performance optimization.

Bio: Taiyun Chi leads the Rice Integrated Systems and Electromagnetics (RISE) Lab, focusing on analog/RF/mmWave circuits and micro-systems design for wireless communication and neuro-engineering applications. Since joining Rice in 2019, his group has received multiple Best Paper awards and nominations, including the IEEE International Solid-State Circuits Conference (ISSCC) Lewis Winner Outstanding Paper Award in 2025 and 2024, the IEEE International Microwave Symposium (IMS) Advanced Practice Paper Award Finalist in 2024 and 2021, the IEEE RFIC Symposium Industry Paper Award Finalist in 2023, the IEEE RFIC Symposium Best Student Paper Award Finalist in 2022, and the IEEE Custom Integrated Circuits Conference (CICC) Best Student Paper Award in 2021. He was a recipient of the NSF

On Thursday, May 21, 2026, the IEEE MTT-S Japan/Kansai/Nagoya Chapters DML (Distinguished Microwave Lectures) lecture was successfully held at the Ookayama Campus of the Institute of Science Tokyo.

We welcomed Dr. Joel Dunsmore of Keysight Technologies as the speaker. Dr. Dunsmore is one of the world-leading researchers specializing in the research and development of vector network analyzers (VNAs) and VNA-based measurements. In recent years, he has been particularly active in the fields of nonlinear measurements, including differential device and mixer measurements, as well as modulation and spectrum measurements.

Speaker: Dr. Joel Dunsmore (Keysight Technologies)

Title: Modern Methods for Component Measurements using Vector Network Analyzers

Abstract: Modern Vector Network Analyzers (VNA) have flexible hardware and software with much higher performance than VNAs of even a few years ago. There are a wide range of measurement applications, beyond simple S-parameters, that a VNA can address, and with precision that cannot be achieved by other test methods. VNAs now act as a multi-functional test system, providing an extremely wide range of device- and signal-characterization capabilities including noise figure, gain-compression, true-mode differential device characterization, two-tone Inter-Modulation Distortion (IMD), phase-noise, mixer and frequency converter gain/phase/delay measurements. Very recently Vector Spectrum Analysis (VSA) capabilities have been added, including measurements of complex modulated signals such as Error Vector Magnitude (EVM), Adjacent Channel Power Ratio (ACPR) and characteristics of Digital Pre-Distortion (DPD). These capabilities, when properly configured, provide the most precise measurements of high-frequency mm-wave and sub-THz modulated signals, beyond the capabilities of stand-alone measurement instruments, as was demonstrated using 20 GHz bandwidth modulated signals at 250 GHz. This lecture illuminated the methods and capabilities for these advanced measurement methods for characterizing microwave components.

Following the lecture, a reception was held with Dr. Dunsmore, providing an opportunity for friendly conversation and a lively exchange of technical insights.

The Okada Laboratory held a welcome party for new members in Kamata.

The new members took on the challenge of introducing themselves in English, and senior members responded in kind with welcome speeches. The B4 students — put on the spot with no time to prepare — held their own admirably in their unfamiliar English speeches.

The anime and games each member had recently been enjoying turned out to be a good window into knowing one another’s personalities.

Six papers from Okada Laboratory have been accepted at the 2026 IEEE Symposium on VLSI Technology and Circuits (VLSI Symposium 2026), to be held on June 14–18, 2026 in Honolulu, Hawaii, USA. The symposium is one of the flagship international conferences in VLSI technology and circuits. The accepted papers cover phased-array radio circuits and a full-duplex transceiver spanning a wide range of frequencies from 2 GHz up to 240–270 GHz, along with a high-efficiency power amplifier.

Minzhe Tang, Ziyuan Ren, Yuxuan Liu, Yilun Chen, Minghao Fan, Dongfan Xu, Haiyun Gu, Zheng Li, Yi Zhang, Jian Pang, Daxu Zhang, Zezheng Liu, Dingxin Xu, Chenxin Liu, Duo Li, Yuncheng Zhang, Chun Wang, Yudai Yamazaki, Sena Kato, Hiroyuki Sakai, Kazuaki Kunihiro, and Kenichi Okada, “A Ka-Band Time-Division Multi-Stream Phased-Array Transmitter with Built-in Spatial Notch Generation for 6G MIMO”

Chun Wang, Olivia Angel Yong, Chenxin Liu, Wenqian Wang, Anyi Tian, Abanob Shahata, Takumi Kojima, Hans Herdian, Yudai Yamazaki, Sunghwan Park, Minzhe Tang, Dongfan Xu, Sena Kato, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, and Kenichi Okada, “240-270 GHz 4x4 Bi-Directional Phased-Array Transceiver with On-Chip Half-Wavelength-Spaced Array and Ultra-Low Power Consumption in 65-nm CMOS”

Minghao Fan, Yilun Chen, Zheng Li, Ziyuan Ren, Minzhe Tang, Junqing Liu, Yuxuan Liu, Dongfan XU, ZeZheng Liu, Yudai Yamazaki, Sena Kato, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, and Kenichi Okada, “A 57-71-GHz CMOS Phased-Array Transceiver with Aperture-Tuning Antenna Achieving 47.9-62.2% EIRP Efficiency Improvement”

Yudai Yamazaki, Ryuji Kinugawa, Takumi Kojima, Takaya Uchino, Anyi Tian, Chenxin Liu, Sunghwan Park, Kotaro Ito, Sena Kato, Chun Wang, Minzhe Tang, Takashi Tomura, Yuncheng Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, and Kenichi Okada, “A 144Gbps D-Band Dual-Polarized MIMO High-Density Phased-Array Transceiver in 65nm CMOS for 6G UE”

Yuncheng Zhang, Duo Li, Zihang Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, and Kenichi Okada, “A Switched Inductor-Capacitor Power Amplifier Supporting 100MHz 256-QAM”

Dongfan Xu, Haiyun Gu, Minzhe Tang, Yuxuan Liu, Ziyuan Ren, Yilun Chen, Minghao Fan, Duo Li, Zheng Li, Yi Zhang, Daxu Zhang, Zezheng Liu, Chun Wang, Sena Kato, Yudai Yamazaki, Hiroyuki Sakai, Yuncheng Zhang, Kazuaki Kunihiro, and Kenichi Okada, “A Reconfigurable 24-28GHz Time-Division Full-Duplex Transceiver with 59dB Self-Interference Rejection over 400MHz”

Institute of Science Tokyo (Science Tokyo) has been ranked 1st in Japan and 20th worldwide in Engineering - Electrical & Electronic in the QS World University Rankings by Subject 2026.

Okada Laboratory conducts advanced research on millimeter-wave and terahertz wireless communication, CMOS integrated circuits, phased arrays, 5G/6G/7G systems, and satellite communications.

As one of the laboratories driving research in electrical and electronic engineering at Science Tokyo, Okada Laboratory will continue to advance next-generation wireless communication and integrated circuit technologies.

QS World University Rankings for Engineering - Electrical and Electronic 2026 | TopUniversities

The rain stopped, and although it was a bit cold, we had a great time.

At the commencement ceremony of Institute of Science Tokyo, two members from our laboratory were selected as representatives.

Yudai Yamazaki was chosen as the representative of doctoral graduates in the Electrical and Electronic Engineering Course, and Kotaro Ito was selected as the representative of undergraduate students in the Department of Electrical and Electronic Engineering.

Congratulations on their graduation!

A JSSC paper by Yudai Yamazaki on developing an ultra-compact phased-array transceiver for 6G applications has been published.

This paper is related to the research result announced on June 13, 2025, “Development of an Ultra-Compact, Low-Power Antenna-Integrated Radio Module in the 150 GHz Band.”

Reference URLs:

https://ieeexplore.ieee.org/document/11418901

https://www.isct.ac.jp/en/news/iig8wa1xp0ny

At ISSCC 2026, Yudai Yamazaki received the Poster Award for his presentation in the Student Research Preview (SRP). Congratulations!

Poster Title:　A High-Power-Density D-Band Phased-Array Transceiver in 65nm CMOS for 6G UE Module

The Department of Electrical and Electronic Engineering will hold graduate school information sessions for those considering admission or further study in the field. The sessions will mainly provide information on the master’s program and introduce our laboratories. Both sessions will be held in a hybrid format (on-site + Zoom).

For details on application procedures, admission requirements, and the official guidelines, please also refer to the University’s admissions webpage:

Admissions

■Event Date and Time

Session 1 (Ookayama)　Friday, March 27, 2026, 13:00–17:00

Session 2 (Suzukakedai)　Friday, May 15, 2026, 13:00–17:00

■Program

13:00–14:00 Graduate Admissions Information Session (Electrical and Electronic Engineering)

14:00–17:00 Laboratory Tours

■Venue

Session 1 (Ookayama)

Ookayama Campus, South Building 2, Lecture Room S2-204 (S221) / Hybrid (Zoom)

Session 2 (Suzukakedai)

Suzukakedai Campus, Building J2, Lecture Room J2-203 (tentative) / Hybrid (Zoom)

■Who Should Attend

Undergraduate and graduate students who plan to apply to graduate school

Those considering admission to the School of Engineering, Department of Electrical and Electronic Engineering

Those wishing to enroll in September 2026 or April 2027

■Capacity

On-site: 150 participants

Online: No limit

■Language

Japanese

■Registration

Please register in advance via the form below.

Session 1 (Ookayama): Application Form

Session 2 (Suzukakedai): Application Form

■Registration Deadline

Registration is open until shortly before each session.

A miniaturized radar chip, developed by researchers at Science Tokyo, advances Integrated Sensing and Communication for Beyond 5G and 6G systems. Measuring just 0.24 mm2 and consuming only 9.8 mW, the compact, low-power device generates high-speed, highly linear chirps by embedding linearization directly into the hardware, overcoming traditional speed-versus-accuracy limits and enabling precise sensing for edge and Internet-of-Things devices.

Speaker: Prof. Hua Wang (ETH, Zurich, Swiss)

Title: AI-Assisted for Radio-Frequency Integrated Circuits at ETH Zurich

Abstract: In recent years, as AI for Science is gaining increasing momentum, there are rapidly growing interest in applying AI tools to facilitate RFIC designs or explore new design spaces. In this seminar talk, I will present a few on-going AI4RF projects at my IDEAS group at ETH Zurich. We will start with our project of AI-assisted template-seeded pixelated design for multi-metal-layer EM structures, which explores a new approach for efficient exploration and exploitation of the design space. Next, we will introduce our transfer learning assisted fast design migration, which potentially enables efficient design migrations over technology nodes and operating frequencies. Finally, we will present out project on top-metal-only RFIC redesigns for fast specs-to-silicon iteration enabled by AI-assisted inverse design. Finally, we will discuss challenges and future directions.

Speaker: Prof. Mehdi Saligane (Brown University, USA)

Title: AI for Chips & Chips for AI

Abstract: The exploding scale of modern applications is stretching yesterday’s integrated-circuit (IC) design flows beyond their limits. This talk presents a unified, open, and highly-automated paradigm—AI for Chips & Chips for AI—that simultaneously (i) harnesses artificial intelligence in EDA to build better silicon and (ii) architects silicon that runs AI better.

AI for Chips - Traditional analog layout still relies on expert heuristics. We introduce Agentic-RL gLayout, a goal-conditioned reinforcement-learning agent that replaces hand-tuned placement and routing with policy-driven planning, action, and self-correction. The agent ingests high-level objectives, observes the evolving layout state, and chooses between primitive commands and high-level macros. Positive rewards track goal attainment; penalties capture DRC violations, area bloat, and parasitics, producing cleaner, compact, and rule-compliant layouts without manual intervention. Built atop open-source engines such as OpenROAD, Open Se Cura, and OpenFASoC, the framework pushes layout quality while democratizing access to sophisticated analog design automation. Chips for AI - Conversely, deploying large language model (LLM) workloads at the edge demands silicon tuned for extreme efficiency. We unveil a hardware–software co-design stack centered on ConSmax, a highly parallel, element-wise alternative to Softmax that slashes latency and energy. By co-optimizing network topology, arithmetic precision, and accelerator micro-architecture, the framework meets sub-millisecond deadlines, preserves privacy, and cuts cloud dependence.

Finally, this talk will walk through an open chip design infrastructure augmented with LLM-guided code, circuit, and layout generation that turns hardware creation into a rapid feedback loop, where AI sharpens the EDA tools, while tailored accelerators speed up AI. Closing the “AI-for-chips, chips-for-AI” cycle should make taping-out test chips possible in weeks instead of years, thus propelling the next wave of semiconductor innovation.

Bio: Mehdi Saligane received the B.S. and M.S. degrees in Electrical Engineering Systems and Industrial Computing from École Polytechnique de Grenoble in 2009, and the M.S. Degree in electrical engineering from the University of Grenoble in 2011, and the Ph.D. degree in Electrical Engineering and Computer Science from the University of Aix-Marseille (IM2NP), France, in 2016. From 2010 to 2015, he was part of the Central Research and Development Group at STMicroelectronics in Crolles, France, focusing on adaptive, ultra-low-power digital design. In 2015, he joined the Michigan Integrated Circuit Laboratory at the University of Michigan, Ann Arbor, MI, USA, as a visiting research investigator. In 2019, he served as a Visiting Researcher at the University of California, San Diego, San Diego, CA, USA. He is a founding member of both the OpenROAD and OpenFASOC Projects. Since 2020, he has been a Research Faculty member at the University of Michigan. In 2024, he joined Google Research as a Visiting Faculty Member, and in 2025, he joined Brown University as an Assistant Professor of Electrical and Computer Engineering. His research interests include secure low-power and energy-efficient IC design, Biosensors, analog/mixed-signal design automation and open-source EDA, and custom architectures for lightweight language model accelerators. Dr. Saligane is the recipient of the 2023 Google Cloud Research Innovators Award and the 2021 Google Research Faculty Award. He served in leadership roles at the CHIPS Alliance from 2020 to 2023, including as Chair of the Analog Working Group and as a member of the Technical Steering Committee. Since 2020, he has served on the IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (TC-OSE) Technical Committee and has been the Chair since 2025. In addition, he co-founded and organizes the SSCS Chipathon Design Contest and the SSCS Code-a-Chip Notebook Competition at ISSCC and VLSI Symposium, fostering student engagement with open-source chip design.

Presentations in ISSCC 2026

Forum Presentation

• Kenichi Okada, “Exploration of 6G FR3 for Coverage, Capacity, and Sensing in Edge AI Era”

Regular Session

• Daxu Zhang, et al., “A 9.7GHz Self-Linearized-VCO-Based FMCW Chirp Generator Achieving 1.56GHz/µs Slope and 0.57µs Duration with 0.094% rms Frequency Error”

Dongfan Xu, Minghao Fan will present their work in Student Research Preview.

Seminar

Speaker: Prof. Jeffrey S. Walling (Virginia Tech, USA)

Title: Bits-to-Waves: Digital RF, mm-Wave and THz Systems to Enable the Next-G

Abstract: Mixer-based transmitters have been dominant for approximately 100 years. However, for more than a decade RF-DACs have demonstrated the ability to combine the functionality of the DAC, upconverter and amplification stages of a transmitter into a single block. The switched-capacitor power amplifier (SCPA) is a versatile RF-DAC that operates in a voltage mode and uses transistors only as switches. This talk provides a tutorial introduction of the SCPA and presents architectural examples that enable both frequency reconfigurability and operation up to mm-Wave, supporting up to 3Gb/s transmission rates. New uses of algorithmic designs for RF passives will also be introduced.

Speaker Bio: Jeff Walling received his BS from University of South Florida and his MS and PhD from University of Washington, all in Electrical Engineering. He has held industrial positions at Motorola, Intel, Qualcomm and Skyworks. His research has primarily focused on circuits for wireless communications and sensing. From 2012 to 2019, he was an assistant, then associate professor at University of Utah. Then he was head of RF transceivers at Tyndall National Institute in Cork, Ireland. Since 2021, he is an associate professor at Virginia Tech. He has served as an associate editor for TCAS-II, TCAS-I and JSSC, and on the technical program committees of the IEEE RFIC, ISSCC and NEWCAS conferences. He is a senior member of the IEEE and has more than 80 papers in peer reviewed conferences and journals.

Two students presented their work in IEEE Asian Solid-State Circuits Conference (A-SSCC), Daejeon, Korea.

Dongfan Xu, Minzhe Tang, Haiyun Gu, Ziyuan Ren, Yilun Chen, Minghao Fan, Yuxuan Liu, Daxu Zhang, Yi Zhang, Zheng Li, Yuncheng Zhang, and Kenichi Okada,

“A Ka-Band Time-Modulated Variable Gain Amplifier with 30-dB Gain Tuning and <2° Phase Variation via Duty Cycle Control”

Sunghwan Park, Yudai Yamazaki, Carrel de Gomez, Chenxin Liu, Jun Sakamaki, Hiroyuki Sakai, Kazuaki Kunihiro, and Kenichi Okada,

“A High-Efficient 154GHz 4TX/4RX FMCW Radar Chipset in 65nm CMOS”

Kenichi Okada“How to cultivate good chip designers” Panel discussion

“Millimeter-Wave Circuit Innovations for 6G and Beyond”

KAIST EE Global Symposium

IEEE/IEIE ICCE Asia“Millimeter-Wave Circuit Innovations for 6G and Beyond”

also presented at Seoul National Univerisity

A picture after paper submission!

We held an OB/OG reunion on Aug. 23th, 2025

If you haven’t received emails from the OB/OG mailing list, please contact us at secretary@ssc.p.isct.ac.jp.

At the 2nd MCRG (Mobile Communication Research Group) Symposium of 2025, Mr. Yudai Yamazaki was recognized as the researcher who delivered the most outstanding poster presentation. Congratulations!

**Poster Title: “**A 150GHz Compact Phased-Array Transceiver for 6G UE"

Prof. Chung-Tse Michael Wu (National Taiwan University) visited our lab!