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The following paper from our laboratory received the IEICE Electronics Express (ELEX) Best Paper Award. The award ceremony was held at the Electronics Society Plenary Session of the 2026 IEICE Society Conference.

Yi Zhang, Minzhe Tang, Dongfan Xu, Jian Pang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, and Kenichi Okada,“A 2.5 dB noise figure 28 GHz current-reused noise-cancelling LNA with gm-boosting in 65 nm CMOS for millimeter-wave MIMO applications,“IEICE Electronics Express, Vol. 22, No. 6, 20250033 (2025).

The paper presents a 28 GHz low-noise amplifier (LNA) in 65 nm CMOS that achieves a 2.5 dB noise figure for millimeter-wave MIMO applications by combining a current-reused noise-cancelling topology with a gm-boosting technique.

Yudai Yamazaki, Assistant Professor in our laboratory, received the IEICE Electronics Society Student Encouragement Award (Field 3: Circuits and Electronics). The award ceremony was held at the Electronics Society Plenary Session of the 2026 IEICE Society Conference.

The award is presented by the IEICE Electronics Society to students who gave outstanding presentations at the Society’s conferences.

Our laboratory held a party to welcome new members, to celebrate members who completed their degrees, and to mark the completion of our paper submissions to ISSCC.

The highlight of the evening was a Mario Kart tournament, in which participants competed in teams. Faculty and students alike enjoyed the games together, and the event was a great opportunity for everyone in the lab to get to know each other better.

On August 22, 2026, we held the summer alumni (OB/OG) reunion of the Matsuzawa, Okada and Shirane Laboratories. Alumni and current members gathered to catch up on each other’s news and the labs’ recent activities, and everyone enjoyed a lively evening together. Thank you to all who attended.

We have developed the world’s first phased-array radio capable of MIMO communication in the 150 GHz band, aimed at 6G (sixth-generation mobile communication systems).

This achievement was presented at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits, held in Honolulu, USA, from June 14 to 18. The paper was also selected as one of ten highlighted circuit papers at the conference, and was featured as the lead paper among them.

Key points

• Developed a phased-array radio capable of sub-terahertz dual-polarized MIMO communication
• Demonstrated ultra-high-speed communication of 144 Gbps through high-density integration of 150 GHz-band bi-directional transmit/receive circuitry
• Expected to enable applications such as indoor XR and telemedicine via 6G mobile communication

Publication

Yudai Yamazaki, Ryuji Kinugawa, Takumi Kojima, Takaya Uchino, Anyi Tian, Chenxin Liu, Sunghwan Park, Kotaro Ito, Sena Kato, Chun Wang, Minzhe Tang, Takashi Tomura, Yuncheng Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, and Kenichi Okada, “A 144Gbps D-Band Dual-Polarized MIMO High-Density Phased-Array Transceiver in 65nm CMOS for 6G UE,” IEEE Symposium on VLSI Technology and Circuits (VLSI Circuits), Honolulu, HI, June 2026.

On Tuesday, July 7, 2026, a site visit for the JST Next-Generation Edge AI Semiconductor Research and Development Program — research theme “Research and Development of Analog-Digital Mixed-Signal Edge AI SoC Design Technology” (Grant Number: JPMJES2515) — was held at the Ookayama Campus of Institute of Science Tokyo.

We welcomed representatives of the Japan Science and Technology Agency (JST) and the program advisors, and introduced the activities and progress of this research and development theme, along with a tour of our research facilities and an exchange of views on the research and development. The visit gave rise to active discussions, and we received valuable advice.

We would like to express our sincere gratitude, and we will continue to move the project forward.

We have succeeded in realizing a two-dimensional phased-array transceiver capable of wireless communication in the terahertz band, implemented entirely in a CMOS integrated circuit — including the antennas and the bi-directional transmit/receive circuitry.

This achievement was presented at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits, held in Honolulu, USA, from June 14 to 18.

Key points

• Realized a 300 GHz-band 2D phased-array transceiver using a low-cost, mass-producible CMOS integrated circuit
• Achieved the world’s first integration of a 300 GHz half-wavelength-spaced 2D 4×4 antenna array together with bi-directional phased-array transmit/receive circuitry on a single all-CMOS chip
• Demonstrated an ultra-low-power, low-cost IC, accelerating the implementation of terahertz-band wireless communication in 6G

Publication

Chun Wang, Olivia Angel Yong, Chenxin Liu, Wenqian Wang, Anyi Tian, Abanob Shehata, Takumi Kojima, Hans Herdian, Yudai Yamazaki, Sunghwan Park, Minzhe Tang, Dongfan Xu, Sena Kato, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, and Kenichi Okada, “A 240-270 GHz 4x4 Bi-Directional Phased-Array Transceiver with On-Chip Half-Wavelength-Spaced Array and Ultra-Low Power Consumption in 65-nm CMOS,” IEEE Symposium on VLSI Technology and Circuits (VLSI Circuits), Honolulu, HI, June 2026.

To realize the ultra-high-speed, large-capacity wireless communication required in the Beyond 5G/6G era, we have developed a broadband phased-array antenna and transceiver IC that supports the entire 5G millimeter-wave band (5G NR FR2-2 n263 band: 57–71 GHz).

This achievement was presented at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits, held in Honolulu, USA, from June 14 to 18.

Key points

• Developed an antenna and transceiver IC that achieves highly efficient, stable communication across the entire 57–71 GHz 5G millimeter-wave band
• An “aperture-tuning antenna” — which optimizes the antenna’s effective radiation aperture at each frequency by adjusting the internal current distribution — is integrated with the transmit/receive circuitry, enabling both wideband operation and a compact, low-loss design
• Expected to contribute to ultra-high-speed, large-capacity communication infrastructure for the Beyond 5G/6G era, as well as next-generation services such as high-definition XR

Publication

Minghao Fan, Yilun Chen, Zheng Li, Ziyuan Ren, Minzhe Tang, Junqing Liu, Yuxuan Liu, Dongfan Xu, ZeZheng Liu, Yudai Yamazaki, Sena Kato, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, and Kenichi Okada, “A 57-71-GHz CMOS Phased-Array Transceiver with Aperture-Tuning Antenna Achieving 47.9-62.2% EIRP Efficiency Improvement,” IEEE Symposium on VLSI Technology and Circuits (VLSI Circuits), Honolulu, HI, June 2026.

To keep pace with the explosive growth in traffic in the Beyond 5G/6G era, we have developed an in-band full-duplex (FD) communication scheme applicable to broadband millimeter-wave communication, along with a wireless IC that implements this scheme.

This achievement was presented at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits, held in Honolulu, USA, from June 14 to 18.

Key points

• Developed a wireless IC featuring a millimeter-wave full-duplex communication scheme that eliminates the need for complex interference-cancellation circuitry
• Achieved effectively simultaneous transmission and reception on the same frequency and at the same time through ultra-high-speed switching faster than the wireless signal period
• Expected to enable ultra-high-speed, low-latency bidirectional communication for applications such as real-time control in smart factories and high-definition XR

Publication

Dongfan Xu, Haiyun Gu, Minzhe Tang, Yuxuan Liu, Ziyuan Ren, Yilun Chen, Minghao Fan, Duo Li, Zheng Li, Yi Zhang, Daxu Zhang, Zezheng Liu, Chun Wang, Sena Kato, Yudai Yamazaki, Hiroyuki Sakai, Yuncheng Zhang, Kazuaki Kunihiro, and Kenichi Okada, “A Reconfigurable 24-28GHz Time-Division Full-Duplex Transceiver with 59dB Self-Interference Rejection over 400MHz,” IEEE Symposium on VLSI Technology and Circuits (VLSI Circuits), Honolulu, HI, June 2026.

Minghao Fan from Okada Laboratory received the Best Poster Award at the 1st MCRG (Mobile Communication Research Group) Workshop of FY2026. His award-winning poster is titled “A 60-GHz CMOS Phased-Array Transceiver with Aperture-Tuning Antenna for EIRP Efficiency Improvement.” Congratulations!

Speaker: Prof. Taiyun Chi (Rice University)

Title: Toward AI-Assisted Analog and RF IC Design Automation

Abstract: LLMs have advanced rapidly over the past three years, with frontier systems now supporting trillion-scale parameter counts, million-token context windows, multimodal inputs/outputs, stronger reasoning, coding, computer use, and agentic workflows. At the same time, the way we work with LLMs has shifted accordingly, from prompt engineering to context engineering, and more recently to harness engineering. These advances and paradigm shifts have enabled many great successes in “AI for X,” especially in coding. This talk will present our group’s recent progress toward integrating LLMs into analog and RF IC design, a field that has conventionally remained manual, time-consuming, and dependent on deep domain expertise. We will discuss what today’s AI systems can do, where they still fail, and which directions appear most promising for analog and RF IC design automation. I will also cover AI techniques beyond LLMs that enable fast design-space exploration and performance optimization.

Bio: Taiyun Chi leads the Rice Integrated Systems and Electromagnetics (RISE) Lab, focusing on analog/RF/mmWave circuits and micro-systems design for wireless communication and neuro-engineering applications. Since joining Rice in 2019, his group has received multiple Best Paper awards and nominations, including the IEEE International Solid-State Circuits Conference (ISSCC) Lewis Winner Outstanding Paper Award in 2025 and 2024, the IEEE International Microwave Symposium (IMS) Advanced Practice Paper Award Finalist in 2024 and 2021, the IEEE RFIC Symposium Industry Paper Award Finalist in 2023, the IEEE RFIC Symposium Best Student Paper Award Finalist in 2022, and the IEEE Custom Integrated Circuits Conference (CICC) Best Student Paper Award in 2021. He was a recipient of the NSF

On Thursday, May 21, 2026, the IEEE MTT-S Japan/Kansai/Nagoya Chapters DML (Distinguished Microwave Lectures) lecture was successfully held at the Ookayama Campus of the Institute of Science Tokyo.

We welcomed Dr. Joel Dunsmore of Keysight Technologies as the speaker. Dr. Dunsmore is one of the world-leading researchers specializing in the research and development of vector network analyzers (VNAs) and VNA-based measurements. In recent years, he has been particularly active in the fields of nonlinear measurements, including differential device and mixer measurements, as well as modulation and spectrum measurements.

Speaker: Dr. Joel Dunsmore (Keysight Technologies)

Title: Modern Methods for Component Measurements using Vector Network Analyzers

Abstract: Modern Vector Network Analyzers (VNA) have flexible hardware and software with much higher performance than VNAs of even a few years ago. There are a wide range of measurement applications, beyond simple S-parameters, that a VNA can address, and with precision that cannot be achieved by other test methods. VNAs now act as a multi-functional test system, providing an extremely wide range of device- and signal-characterization capabilities including noise figure, gain-compression, true-mode differential device characterization, two-tone Inter-Modulation Distortion (IMD), phase-noise, mixer and frequency converter gain/phase/delay measurements. Very recently Vector Spectrum Analysis (VSA) capabilities have been added, including measurements of complex modulated signals such as Error Vector Magnitude (EVM), Adjacent Channel Power Ratio (ACPR) and characteristics of Digital Pre-Distortion (DPD). These capabilities, when properly configured, provide the most precise measurements of high-frequency mm-wave and sub-THz modulated signals, beyond the capabilities of stand-alone measurement instruments, as was demonstrated using 20 GHz bandwidth modulated signals at 250 GHz. This lecture illuminated the methods and capabilities for these advanced measurement methods for characterizing microwave components.

Following the lecture, a reception was held with Dr. Dunsmore, providing an opportunity for friendly conversation and a lively exchange of technical insights.

The Okada Laboratory held a welcome party for new members in Kamata.

The new members took on the challenge of introducing themselves in English, and senior members responded in kind with welcome speeches. The B4 students — put on the spot with no time to prepare — held their own admirably in their unfamiliar English speeches.

The anime and games each member had recently been enjoying turned out to be a good window into knowing one another’s personalities.

Six papers from Okada Laboratory have been accepted at the 2026 IEEE Symposium on VLSI Technology and Circuits (VLSI Symposium 2026), to be held on June 14–18, 2026 in Honolulu, Hawaii, USA. The symposium is one of the flagship international conferences in VLSI technology and circuits. The accepted papers cover phased-array radio circuits and a full-duplex transceiver spanning a wide range of frequencies from 2 GHz up to 240–270 GHz, along with a high-efficiency power amplifier.

Minzhe Tang, Ziyuan Ren, Yuxuan Liu, Yilun Chen, Minghao Fan, Dongfan Xu, Haiyun Gu, Zheng Li, Yi Zhang, Jian Pang, Daxu Zhang, Zezheng Liu, Dingxin Xu, Chenxin Liu, Duo Li, Yuncheng Zhang, Chun Wang, Yudai Yamazaki, Sena Kato, Hiroyuki Sakai, Kazuaki Kunihiro, and Kenichi Okada, “A Ka-Band Time-Division Multi-Stream Phased-Array Transmitter with Built-in Spatial Notch Generation for 6G MIMO”

Chun Wang, Olivia Angel Yong, Chenxin Liu, Wenqian Wang, Anyi Tian, Abanob Shahata, Takumi Kojima, Hans Herdian, Yudai Yamazaki, Sunghwan Park, Minzhe Tang, Dongfan Xu, Sena Kato, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, and Kenichi Okada, “240-270 GHz 4x4 Bi-Directional Phased-Array Transceiver with On-Chip Half-Wavelength-Spaced Array and Ultra-Low Power Consumption in 65-nm CMOS”

Minghao Fan, Yilun Chen, Zheng Li, Ziyuan Ren, Minzhe Tang, Junqing Liu, Yuxuan Liu, Dongfan XU, ZeZheng Liu, Yudai Yamazaki, Sena Kato, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, and Kenichi Okada, “A 57-71-GHz CMOS Phased-Array Transceiver with Aperture-Tuning Antenna Achieving 47.9-62.2% EIRP Efficiency Improvement”

Yudai Yamazaki, Ryuji Kinugawa, Takumi Kojima, Takaya Uchino, Anyi Tian, Chenxin Liu, Sunghwan Park, Kotaro Ito, Sena Kato, Chun Wang, Minzhe Tang, Takashi Tomura, Yuncheng Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, and Kenichi Okada, “A 144Gbps D-Band Dual-Polarized MIMO High-Density Phased-Array Transceiver in 65nm CMOS for 6G UE”

Yuncheng Zhang, Duo Li, Zihang Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, and Kenichi Okada, “A Switched Inductor-Capacitor Power Amplifier Supporting 100MHz 256-QAM”

Dongfan Xu, Haiyun Gu, Minzhe Tang, Yuxuan Liu, Ziyuan Ren, Yilun Chen, Minghao Fan, Duo Li, Zheng Li, Yi Zhang, Daxu Zhang, Zezheng Liu, Chun Wang, Sena Kato, Yudai Yamazaki, Hiroyuki Sakai, Yuncheng Zhang, Kazuaki Kunihiro, and Kenichi Okada, “A Reconfigurable 24-28GHz Time-Division Full-Duplex Transceiver with 59dB Self-Interference Rejection over 400MHz”

Institute of Science Tokyo (Science Tokyo) has been ranked 1st in Japan and 20th worldwide in Engineering - Electrical & Electronic in the QS World University Rankings by Subject 2026.

Okada Laboratory conducts advanced research on millimeter-wave and terahertz wireless communication, CMOS integrated circuits, phased arrays, 5G/6G/7G systems, and satellite communications.

As one of the laboratories driving research in electrical and electronic engineering at Science Tokyo, Okada Laboratory will continue to advance next-generation wireless communication and integrated circuit technologies.

QS World University Rankings for Engineering - Electrical and Electronic 2026 | TopUniversities

The rain stopped, and although it was a bit cold, we had a great time.

At the commencement ceremony of Institute of Science Tokyo, two members from our laboratory were selected as representatives.

Yudai Yamazaki was chosen as the representative of doctoral graduates in the Electrical and Electronic Engineering Course, and Kotaro Ito was selected as the representative of undergraduate students in the Department of Electrical and Electronic Engineering.

Congratulations on their graduation!

A JSSC paper by Yudai Yamazaki on developing an ultra-compact phased-array transceiver for 6G applications has been published.

This paper is related to the research result announced on June 13, 2025, “Development of an Ultra-Compact, Low-Power Antenna-Integrated Radio Module in the 150 GHz Band.”

Reference URLs:

https://ieeexplore.ieee.org/document/11418901

https://www.isct.ac.jp/en/news/iig8wa1xp0ny

At ISSCC 2026, Yudai Yamazaki received the Poster Award for his presentation in the Student Research Preview (SRP). Congratulations!

Poster Title:　A High-Power-Density D-Band Phased-Array Transceiver in 65nm CMOS for 6G UE Module

The Department of Electrical and Electronic Engineering will hold graduate school information sessions for those considering admission or further study in the field. The sessions will mainly provide information on the master’s program and introduce our laboratories. Both sessions will be held in a hybrid format (on-site + Zoom).

For details on application procedures, admission requirements, and the official guidelines, please also refer to the University’s admissions webpage:

Admissions

■Event Date and Time

Session 1 (Ookayama)　Friday, March 27, 2026, 13:00–17:00

Session 2 (Suzukakedai)　Friday, May 15, 2026, 13:00–17:00

■Program

13:00–14:00 Graduate Admissions Information Session (Electrical and Electronic Engineering)

14:00–17:00 Laboratory Tours

■Venue

Session 1 (Ookayama)

Ookayama Campus, South Building 2, Lecture Room S2-204 (S221) / Hybrid (Zoom)

Session 2 (Suzukakedai)

Suzukakedai Campus, Building J2, Lecture Room J2-203 (tentative) / Hybrid (Zoom)

■Who Should Attend

Undergraduate and graduate students who plan to apply to graduate school

Those considering admission to the School of Engineering, Department of Electrical and Electronic Engineering

Those wishing to enroll in September 2026 or April 2027

■Capacity

On-site: 150 participants

Online: No limit

■Language

Japanese

■Registration

Please register in advance via the form below.

Session 1 (Ookayama): Application Form

Session 2 (Suzukakedai): Application Form

■Registration Deadline

Registration is open until shortly before each session.