Latest News

Yamazaki-san won IEEE SSCS Japan Chapter VDEC Design Award!!

Prof. Inchan Ju visited our lab!

Congratulations on completing your Master’s degree! Keep up the good work in your PhD study!

Xi FU, a doctoral course student, won this-year’s IEEE SSCS Predoctoral Achievement Award. This award is for recognizing his outstanding achievement based on the aveacademic record and promise, quality of publications.

New transceiver design capable of both transmission and reception at frequencies over 100 GHz and at 112 Gb/s data rate could pave the way to 6G technologies, as reported by scientists at Tokyo Tech. By effectively suppressing the self-interference caused by the transmission signal leaking into the receiver, the proposed architecture reaches unprecedented data rates while maintaining a surprisingly compact size.

Prof. Bogdan Staszewski came to our lab at June 9th, 2023! Welcome!!!

Prof. Kenneth O came to our lab at June 7th, 2023! Welcome!!!

Dr. Bodhisatwa Sadhu, from IBM, visited our laboratory! Thank you! image

Prof. Donald Lie came to our lab at March 29th, 2023! Welcome!!!

Cherry-blossom viewing!

Jitters are a common shortcoming of modern electronic devices using a high-frequency digital signal. While oversampling phase-locked loops (OSPLLs) can expand the loop bandwidth, effectively reducing jitter, conventional OSPLLs suffer from high jitter in noisy signal peak areas. Tokyo Tech researchers have instead suggested and demonstrated a non-uniform OSPLL that can efficiently suppress jitter through adaptive loop gain calibration. This novel architecture leads to more economical and power-efficient devices than conventional OSPLLs.

More than 40 lab members and alumni gathered after ISSCC plenary talk by Prof. Matsuzawa!

Publication in ISSCC 2023. Regular Session Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration” Dongwon You, et al., “A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler” Xi Fu, et al., “A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low Earth Orbit Small Satellite Constellation” Plenary Talk Prof. Matsuzawa, “Shape the World With Mixed-Signal Integrated Circuits – Past, Present, and Future” Chun Wang and Dingxin Xu will present their work in Student Research Preview.

Prof. Emanuel Cohen came to our lab at November 29th, 2022! Welcome!!!

Publication in ISSCC 2022. Regular Session Jian Pang, et al., “A Power-Efficient 24-71GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36-dB Inter-Band Blocker Rejection for 5G NR” Xi Fu, et al., “A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation” Michihiro Ide and Dongwon You will present their work in Student Research Preview.

Publication in ISSCC 2021. Regular Session Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth” Ibrahim Abdo, et al., “A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS” Zheng Li, Zheng Sun, and Michihiro Ide will present their work in Student Research Preview.

Prof. Fa Dai, South China University of Technology (SCUT), came to our lab at November 8th, 2019! Welcome!!! 1108_1

Prof. Tsung-Hsien Lin, National Taiwan University (NTU), came to our lab at October 25th, 2019! IMG_20191025_175824

Prof. Kofi Makinwa, TU Delft, came to our lab!! IMG_20190801_182340

Great talk from Prof. Nan SUN, UT Austin! New Ingredients in the Pot - Rethink Analog IC Design -