Novel Architecture Can Reduce Noise-Induced Jitters in Digital Technology

Jitters are a common shortcoming of modern electronic devices using a high-frequency digital signal. While oversampling phase-locked loops (OSPLLs) can expand the loop bandwidth, effectively reducing jitter, conventional OSPLLs suffer from high jitter in noisy signal peak areas. Tokyo Tech researchers have instead suggested and demonstrated a non-uniform OSPLL that can efficiently suppress jitter through adaptive loop gain calibration. This novel architecture leads to more economical and power-efficient devices than conventional OSPLLs.