VLSI Circuit Symposium 2019 Paper Acceptance

We got 1 paper accepted to VLSI Circuit Symposium 2019.

(Haosheng Zhang)“0.2mW 70 fsrms-jitter injection-locked PLL using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur”