2 papers accepted in VLSI Circuits!

Two papers have been accepted for presentation in VLSI Circuits!

10-1: A. T. Narayanan, et al.,"A Pulse-Tail-Feedback VCO Achieving FoM of 195dBc/Hz with Flicker Noise Corner of 700Hz“This paper proposes a pulse-tail-feedback technique for improving both 1/f2 and 1/f3 noises. The proposed VCO has separated tail transistors driven by inverters with rail-to-rail voltage swing. The tail transistor has an impulse shaped current waveform to improve FoM, and the flicker noise up-conversion is reduced by the switching operation. A prototype of the proposed VCO is implemented in 180nm CMOS, and the VCO achieves an FoM of 195dBc/Hz from 10kHz-10MHz offset with a flicker noise corner of 700Hz at 4.55GHz oscillation. 23-1: Y. Wang, et al.,”A 100mW 3.0 Gb/s Spectrum Efficient 60 GHz Bi-Phase OOK CMOS Transceiver“A novel high-data-rate low-power spectrum-efficient 60GHz Bi-Phase-On-Off-Keying (BPOOK) transceiver is presented for indoor short-range IoT application targeting IEEE 802.11ad/WiGig standard. By employing bi-phase encoder and doublebalanced mixer, the BPOOK transmitter spectrum is efficient to be compliant with 2-channel bonding spectrum mask. The proposed 60GHz OOK transceiver is fabricated in 65nm CMOS, achieves 3.0 Gb/s data-rate and -46 dBm sensitivity, while consuming a power of 100mW including the on-chip 60GHz synthesizer.

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