VLSI Circuits

Chenさんが，京都で開催中のVLSI Circuitsで発表しました。

A 9.35-ENOB, 14.8 fJ/Conv.-Step Fully-Passive Noise-Shaping SAR ADC, Z. Chen, M. Miyahara and A. Matsuzawa, Tokyo Institute of Technology, JapanThis paper presents an opamp-free solution to implement noise shaping in a successive approximation register analog-to-digital convertor. The comparator noise, incomplete settling error of digital-to-analog convertor and mismatch are alleviated. Designed in a 65 nm CMOS technology, the prototype realizes 58 dB SNDR at 50 MS/s sampling frequency. It consumes 120.7 μW from a 0.8 V supply and achieves a FoM of 14.8 fJ per conversion step.